The present invention relates to an architecture for registers or memory that contributes to reduced power consumption of integrated circuits. More particularly, the register architecture permits for disabling of selective portions of a register in the presence of narrow width data.
Issues of power consumption have become increasingly important for the design of integrated circuits. The power consumption of integrated circuits, particularly that of processors, has increased over the years with the historical increase clock speeds. Modern processors now consume so much power that the heat generated by the processors has become destructive. The increase in power consumption also contributes to reduced battery life in mobile computing applications.
Power management techniques are commonplace in the modern computer. Users of domestic personal computers recognize that computer monitors, disk drives and the like are disabled when not in use. However, such techniques are not able to keep pace with the ever increasing power demands made by newer generations of integrated circuits. Accordingly, there remains a need in the art for an integrated circuit architecture that contributes to reduced power consumption of the integrated circuit.
Embodiments of the present invention provide a register having a plurality of payload portions, some of them being selectively disabled.